DBC(ID:1954/dbc001)

Data-parallel Bit-serial C 

for Data-parallel Bit-serial C

Based on MPL

Supercomputing Res. Center, Bowie, MD
Related languages
MPL => DBC   Based on
References:
  • Gokhale, M. Minnich, R. "FPGA computing in a data parallel C" Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, 1993. pp94-101 view details Abstract: The authors demonstrate a new technique for automatically synthesizing digital logic from a high level algorithmic description in a data parallel language. The methodology has been implemented using the Splash 2 reconfigurable logic arrays for programs written in Data-parallel Bit-serial C (dbC). The translator generates a VHDL description of a SIMD processor array with one or more processors per Xilinx 4010 FPGA. The instruction set of each processor is customized to the dbC program being processed. In addition to the usual arithmetic operations, nearest neighbor communication, host-to-processor communication, and global reductions are supported
    External link: Online copy
  • Jang Don Kim "Implementing Data Parallel C on National's Adaptive Processing Architecture" MASPLAS '96 Mid-Atlantic Student Workshop on Programming Languages and Systems Saturday, April 27, 1996 SUNY at New Paltz view details Abstract: The existence of reconfigurable logic arrays has opened the doors to inexpensive customized computing. By loading a configuration bit stream representing any type of virtual circuit onto the reconfigurable logic array, the array can be used to extend the instruction set or act as a parallel co-processor to a conventional processor. The virtual circuit that is loaded onto the array could implement cumbersome and time-consuming computations freeing up the processor to perform other tasks.

    Reconfigurable logic technology has proceeded at a steady pace; however, the software to support the creation of the configuration bit streams, which make the use of reconfigurable logic possible, has lagged far behind. A programmer should be able to write software in a high-level language and have the compiler create the bit streams necessary to implement the appropriate instructions on the logic array for the specific program at hand.

    Data-parallel bit-serial C (dbC) is an attempt at creating such a high-level language. dbC is a data parallel language which has extensions to ANSI C that are implemented on a reconfigurable logic array. When a dbC program is compiled, a VHDL description of a SIMD processor array is created with each processor having the ability to perform only those operations which will specifically be used in the program being compiled. The VHDL is then synthesized to create the configuration bit stream which is subsequently loaded onto the array. The SIMD array has the capacity to perform arithmetic operations and global reductions as well as nearest neighbor and host-to-processor communication.

    This paper will describe dbC, its mapping to previous platforms, and its mapping to National's Adaptive Processing Architecture (NAPA), a PCI bus based parallel system whose reconfigurable logic elements consist of Multi Chip Modules composed of National Semiconductor CLAy FPGAs. External link: Online copy
  • Gordon, Howard "Compilers on High Performance Computers" March 12, 1999 view details External link: Online copy Extract: data-parallel bit-serial C compiler

    data-parallel bit-serial C compiler



    • ANSI C superset
    • Tightly synchronous model of parallel
      computation SIMD
    • Compiles for both parallel and serial
      domains
    • Arbitrary bit length objects are
      first class in parallel domain
    • Portable Implementation

    PIM/TERASYS/TWIST



    • PIM, Processor In Memory, a chip
      developed at IDA Center for Computing Sciences (CCS), formally Supercomputer
      Research Center (SRC) for use on Agency applications.
    • TERASYS, a workstation with PIM chips
      which is programed in a SIMD fashion.
    • TWIST, a subroutine library callable
      from a C program for running microcode on a TERASYS workstation.
    • The dbC compiler outputs calls to a
      generic SIMD libraries of which TWIST is one.

    dbC Design Goals




    • Simple programming model and easy to
      use
    • Efficient data parallel computation
      on SIMD machines
    • Support computation on arbitrary bit
      length integer in the parallel domain
    • Generated code should be portable, so
      that it can run easily on different platforms
    • dbC has been operational since 1992
      and with Twist, the Terasys library, since summer of 1993.

    A Joint Effort






















    dbC Compiler

    Maya Gokhale, David Sarnoff Research
    Center

    Phil Pfeiffer, East Stroudsburg University

    Don Becker, CESDIS

    Lori Pollock, University of Delaware

    Howard Gordon, NSA


    Manual

    Judith Schlesinger, SRC

    Simulation Library

    Aaron Marks, David Sarnoff Research
    Center

    Twist Library

    Dan Kopetzky, SRC


    Optimizations

    Steve Correll, Red Hot Pepper


    Clusters

    Ron Minnich, David Sarnoff Research
    Center

    Standards Activities



    • Howard Gordon and Maya Gokhale
      participated in the Data Parallel C Extensions (DPCE) subgroup of ANSI Numerical
      C Extensions Group (NCEG) of X3J11.



    • We submitted a proposal on Bit
      Oriented extension which outline the bit extension in dbC in September 1993.



    • We proposed that the extensions be
      incorporated as optional extensions to Data Parallel C, which would provide a
      standard to vendors.



    • As a result of this activity BIT DATA
      TYPES is mentioned in the Data Parallel C Extensions paper which was presented
      to Numerical C Extensions Group of X3J11 in December 1994.


    Resources
    • Advanced Software Technologies at NSA
      ...the DBC bit serial data parallel C compiler for the joint Cray Computer/NSA Cray-3/PIM system...external link