DEL(ID:2356/del001)

Variable instruction set abstract interpreter 

Directly Executed Language (DEL) is executedby a DEL interpreter which resides as a microprogram on the host. Because of the direct correspondence to the high-level language, the DEL interpreter is dedicated to a specificDEL instruction set. However, instruction sets for other HLLs and the corresponding DEL interpreter may be realised by substituting the microprogram. The HLL source program is con-verted to the DEL instructions by a simple one-to-one translation, corresponding to the Type A architecture of the above categories. Other intermediate program representations and image architectures have been described for avariety of high-level languages. Examples are M-code for Modula, P-code for Pascal, threaded code for Forth and Basic, the SECD-machine for Lisp, and the Warren Abstract Machine(WAM) for Prolog.
Related languages
DEL => DELtran   Implementation
References:
  • Wallach, Walter A. Jr "High performance emulation" Report Number: CSL-TR-75-102 Stanford University, Computer Systems Laboratory November 1975 view details Abstract: The Stanford EMMY is examined as an emulation engine. Using the 360 emulator and the DELtran interpreter as examples, the performance of the current EMMY architecture is examined as a high performance emulation vehicle. The problems of using a sequential, vertically organized processor for high speed emulation are developed and discussed. A flexible control structure for high speed emulation studies is derived from an existing high performance processor. This structure issues a stream of microinstructions to a central command bus, allowing user-defined execution resources to execute them in overlapped fashion. These execution resources may be added or deleted with little or no processor rewiring. pdf
  • Flynn, Michael J. et al "The Stanford emulation laboratory " Stanford University, Computer Systems Laboratory Report Number: CSL-TR-76-118 June 1976 view details Abstract:

    The Stanford Emulation Laboratory is designed to support general research in the area of emulation. Central to the laboratory is a universal host machine, the EMMY, which has been designed specifically to be an unbiased, yet efficient host for a wide range of target machine architectures. Microstore in the EMMY is dynamically microprogrammable and thus is used as the primary data storage resource of the emulator. Other laboratory equipment includes a reconfigurable main memory system and an independent control processor to monitor emulation experiments. Laboratory software, including two microassemblers, is briefly described. Three laboratory applications are described: (1) A conventional target machine emulation (a system 360), (2) 'microscopic' examination of emulated target machine I-streams, and (3) Direct execution of a high level language (Fortran II).
    pdf
  • Hoevel, Lee and Michael J. Flynn "A theory of interpretive architectures: some notes on DEL design and a Fortran case study" Stanford University, Computer Systems Laboratory Report Number: CSL-TR-79-171 February 1979 view details Abstract: An interpretive architecture is a program representation that peculiarly suits a particular high level language or class of languages. The architecture is a program representation which we call a directly executed language (DEL). In a companion paper we have explored the theory involved in the creation of ideal DEL forms and have analyzed how some traditional instruction sets compare to this measure. This paper is an attempt to develop a reasonably comprehensive theory of DEL synthesis. By assuming a flexible interpretation oriented host machine, synthesis involves three particular areas: (1) sequencing; both between image machine instructions and within the host interpreter, (2) action rules including both format for transformation and operation invoked, and finally, (3) the name space which includes both name structure and name environment. A complete implementation of a simple version of FORTRAN is described in the appendix of the paper. This DEL for FORTRAN called DELtran comes close to achieving the ideal program measures. pdf
  • Flynn. M.J. Directions and issues in architecture and language. IE E EComputer, 13(10):5-22, October 1980. view details
  • Wedig, Robert G. "Dynamic detection of concurrency in do-loops using ordering matrices" Stanford University, Computer Systems Laboratory Report Number: CSL-TR-81-209 May 1981 view details Abstract: This paper describes the data structures and techniques used in dynamically detecting concurrency in Directly Executed Language (DEL) instruction streams. By dynamic detection, it is meant that these techniques are designed to be used at run time with no special source manipulation or preprocessing required to perform the detection. An abstract model of a concurrency detection structure called an ordering matrix is presented. This structure is used, with two other execution vectors, to represent the dependencies between instructions and indicate where potential concurrency exists. An algorithm is developed which utilizes the ordering matrix to detect concurrency within determinate DO-loops. It is then generalized to detect concurrency in arbitrary del instruction streams.
    pdf
  • Stanford University, Computer Systems Laboratory Report Number: CSL-TR-82-231 February 1982 Wedig, Robert G. "Dynamic detection of concurrency in DEL instruction streams" view details Abstract: Detection of concurrency in Directly Executed Languages (DEL) is investigated. It is theorized that if DELs provide a minimal time -space execution of serial programs, then concurrency detection of such instruction streams approaches the minimum execution time possible for a single task without resorting to algorithm restructuring or source manipulation. It is shown how DEL encodings facilitate the detection of concurrency by allowing early decoding and explicity detection of dependency information. The decoding and dependency algorithms as applied to DELs are developed in detail. Concurrency structures are presented which facilitate the detection process. Since all concurrency is capable of exploitation as soon as it is known that the code is to be executed, i.e., the result of the branch is known, it is proven that all explicit parallelism can be detected and exploited using the techniques developed.

    pdf
  • Donald Alpert "Data buffers for execution architectures" Stanford University, Computer Systems Laboratory Report Number: CSL-TR-83-250 November 1983 view details Abstract: Directly Executed Language (DEL) architectures are derived from idealized representations of high-level languages. DEL architectures show dramatic reduction in the number of instructions and memory references executed when compared to traditional architectures, offering the design considerations for the data buffer in a DEL microprocessor. Simulation techniques were used to evaluate the performance of different sized buffers for a set of Pascal test programs. The results show that a buffer with 256 words typically faults on less than 5% of storage allocations.
    pdf
  • M. J. Flynn and L. W. Hoevel. "Execution architecture: The DELtran experiment." view details
          in IEEE Transactions on Computers 32(2) February 1983 view details
  • Flynn, M. J. and Hoevel, L. W. "Measures of ideal execution architectures" pp356-369 view details
          in IBM Journal of Research and Development, 28(4), July 1984 view details
  • Ganapathi et al "Reverse synthesis compilation for architectural research" Stanford University, Computer Systems Laboratory Report Number: CSL-TR-84-257 March 1984 view details Abstract: This paper discusses the development of compilation strategies for DEL architectures and tools to assist in the evaluation of their efficiency. Compilation is divided into a series of independent simpler problems. To explore optimization of code for DEL compilers, two intermediate representations are employed. One of these representations is at a lower level than target machine instructions. Machine-independent optimization is performed on this intermediate representation. The other intermediate representation has been specifically designed for compiler retargetability It is at a higher level than the target machine. Target code generation is performed by reverse synthesis followed by attributed parsing. This technique demonstrates the feasibility of using automated table-driven code generation techniques for inflexible architectures.
    pdf
          in IBM Journal of Research and Development, 28(4), July 1984 view details
  • Peter M. Borst Thesis Karlsruhe May, 1995 "Towards an Architecture for WAVEInterpretation in Open Distributed Systems " view details
          in IBM Journal of Research and Development, 28(4), July 1984 view details