DSPLD(ID:7488/)

for Digital Simulation Program for Logic Design

Martin Marietta Corp simulation system
References:
  • [Martin Marietta Corp., Baltimore, Md] Digital Simulation Program for Logic Design M70-10244 view details Abstract: The program was developed to verify logic design implemented with digital integrated circuits and simultaneously perform worst case analysis of circuit time delays. Output is a timing chart and a logic element fanout count. The approach was to model individual logic elements, and allow for the connection aspect through input data. Built into the program are clock and clear signals. Variable input signals can be supplied to the circuit.

          in Computer Program Abstracts Cumulative Issue July 15, 1969 -- July 15, 1971 view details